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| DS90LV004 4-Channel LVDS Buffer/Repeater with Pre-Emphasis September 2005 DS90LV004 4-Channel LVDS Buffer/Repeater with Pre-Emphasis General Description The DS90LV004 is a four channel 1.5 Gbps LVDS buffer/ repeater. High speed data paths and flow-through pinout minimize internal device jitter and simplify board layout, while configurable pre-emphasis overcomes ISI jitter effects from lossy backplanes and cables. The differential inputs interface to LVDS, and Bus LVDS signals such as those on National's 10-, 16-, and 18- bit Bus LVDS SerDes, as well as CML and LVPECL. The differential inputs are internally terminated with a 100 resistor to improve performance and minimize board space. The repeater function is especially useful for boosting signals for longer distance transmission over lossy cables and backplanes. Features n 1.5 Gbps data rate per channel n Configurable pre-emphasis drives lossy backplanes and cables n Low output skew and jitter n Hot plug protection n LVDS/CML/LVPECL compatible input, LVDS output n On-chip 100 input termination n 15 kV ESD protection n Single 3.3V supply n Very low power consumption n Industrial -40 to +85C temperature range n Small TQFP Package Footprint n Evaluation Kit Available n See SCAN90004 for JTAG-enabled version 20146601 20146602 DS90LV004 Block Diagram Pinout - Top View (c) 2005 National Semiconductor Corporation DS201466 www.national.com DS90LV004 Pin Descriptions Pin Name IN0+ IN0- IN1+ IN1- IN2+ IN2- IN3+ IN3- OUT0+ OUT0- OUT1+ OUT1- OUT2+ OUT2- OUT3+ OUT3PWDN PEM0 PEM1 POWER VDD 3, 4, 5, 7, 10, 11, 27, 28, 29, 32, 33, 34 8, 9, 17, 18, 23, 24, 25, 26, 37, 38, 43, 44 6, 30, 31, 35, 36 I, Power VDD = 3.3V, 5% TQFP Pin Number 13 14 15 16 19 20 21 22 48 47 46 45 42 41 40 39 12 1 2 I/O, Type Description DIFFERENTIAL INPUTS I, LVDS I, LVDS I, LVDS I, LVDS Channel 0 inverting and non-inverting differential inputs. Channel 1 inverting and non-inverting differential inputs. Channel 2 inverting and non-inverting differential inputs. Channel 3 inverting and non-inverting differential inputs. DIFFERENTIAL OUTPUTS O, LVDS O, LVDS O, LVDS O, LVDS Channel 0 inverting and non-inverting differential outputs. (Note 1) Channel 1 inverting and non-inverting differential outputs. (Note 1) Channel 2 inverting and non-inverting differential outputs. (Note 1) Channel 3 inverting and non-inverting differential outputs. (Note 1) DIGITAL CONTROL INTERFACE I, LVTTL I, LVTTL A logic low at PWDN activates the hardware power down mode. Pre-emphasis Control Inputs (affects all Channels) GND I, Power Ground N/C No Connect Note 1: The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS90LV004 device have been optimized for point-to-point backplane and cable applications. www.national.com 2 DS90LV004 Absolute Maximum Ratings (Note 2) Supply Voltage (VDD) CMOS Input Voltage LVDS Receiver Input Voltage LVDS Driver Output Voltage LVDS Output Short Circuit Current Junction Temperature Storage Temperature Lead Temperature (Solder, 4sec) Max Pkg Power Capacity @ 25C Thermal Resistance (JA) Package Derating above +25C ESD Last Passing Voltage HBM, 1.5k, 100pF -0.3V to +4.0V -0.3V to (VDD+0.3V) -0.3V to (VDD+0.3V) -0.3V to (VDD+0.3V) +40 mA +150C -65C to +150C 260C 1.64W 76C/W 13.2mW/C 15 kV EIAJ, 0, 200pF 250V Recommended Operating Conditions Supply Voltage (VCC) Input Voltage (VI) (Note 3) Output Voltage (VO) Operating Temperature (TA) Industrial -40C to +85C 3.15V to 3.45V 0V to VCC 0V to VCC Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of products outside of recommended operation conditions. Note 3: VID max < 2.4V Electrical Characteristics Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Conditions Min Typ (Note 4) Max Units LVTTL DC SPECIFICATIONS (PWDN, PEM0, PEM1) VIH VIL IIH IIL CIN1 VCL VTH VTL VID VCMR CIN2 IIN High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance Input Clamp Voltage Differential Input High Threshold (Note 5) Differential Input Low Threshold (Note 5) Differential Input Voltage Input Capacitance Input Current VIN = VDD = VDDMAX VIN = VSS, VDD = VDDMAX Any Digital Input Pin to VSS ICL = -18 mA VCM = 0.8V to 3.4V, VDD = 3.45V VCM = 0.8V to 3.4V, VDD = 3.45V VCM = 0.8V to 3.4V, VDD = 3.45V IN+ or IN- to VSS VIN = 3.45V, VDD = VDDMAX VIN = 0V, VDD = VDDMAX -10 -10 -100 100 0.05 3.5 +10 +10 -1.5 2.0 GND -10 -10 3.5 -0.8 VDD 0.8 +10 +10 V V A A pF V LVDS INPUT DC SPECIFICATIONS (INn) 0 0 2400 3.40 100 mV mV mV V pF A A Common Mode Voltage Range VID = 150 mV, VDD = 3.45V 3 www.national.com DS90LV004 Electrical Characteristics Symbol Parameter (Continued) Over recommended operating supply and temperature ranges unless other specified. Conditions Min Typ (Note 4) Max Units LVDS OUTPUT DC SPECIFICATIONS (OUTn) VOD VOD VOS VOS IOS COUT2 ICC Differential Output Voltage, 0% Pre-emphasis (Note 5) Change in VOD between Complementary States Offset Voltage (Note 6) Change in VOS between Complementary States Output Short Circuit Current Output Capacitance Supply Current OUT+ or OUT- Short to GND OUT+ or OUT- to GND when TRI-STATE All inputs and outputs enabled and active, terminated with differential load of 100 between OUT+ and OUT-. PWDN = L RL = 100 between OUT+ and OUT- 250 -35 1.05 -35 -60 5.5 1.18 500 600 35 1.475 35 -90 mV mV V mV mA pF SUPPLY CURRENT (Static) 117 140 mA ICCZ Supply Current - Power Down Mode Differential Low to High Transition Time Differential High to Low Transition Time Differential Low to High Propagation Delay Differential High to Low Propagation Delay Pulse Skew Output Channel to Channel Skew Jitter (0% Pre-emphasis) (Note 7) LVDS Output Enable Time LVDS Output Disable Time 2.7 6 mA SWITCHING CHARACTERISTICS -- LVDS OUTPUTS tLHT tHLT tPLHD tPHLD tSKD1 tSKCC tJIT Use an alternating 1 and 0 pattern at 200 Mbps, measure between 20% and 80% of VOD. 210 210 Use an alternating 1 and 0 pattern at 200 Mbps, measure at 50% VOD between input to output. 2.0 2.0 |tPLHD-tPHLD| Difference in propagation delay (tPLHD or tPHLD) among all output channels. RJ - Alternating 1 and 0 at 750 MHz (Note 8) DJ - K28.5 Pattern, 1.5 Gbps (Note 9) TJ - PRBS 223-1 Pattern, 1.5 Gbps (Note 10) tON tOFF Time from PWDN to OUT change from TRI-STATE to active. Time from PWDN to OUT change from active to TRI-STATE. 25 50 1.1 43 35 300 300 3.2 3.2 80 125 1.5 62 85 300 12 ps ps ns ns ps ps psrms psp-p psp-p ns ns Note 4: Typical parameters are measured at VDD = 3.3V, TA = 25C. They are for reference purposes, and are not production-tested. Note 5: Differential output voltage VOD is defined as ABS(OUT+-OUT-). Differential input voltage VID is defined as ABS(IN+-IN-). Note 6: Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states. Note 7: Jitter is not production tested, but guaranteed through characterization on a sample basis. Note 8: Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = VID = 500mV, 50% duty cycle at 750MHz, tr = tf = 50ps (20% to 80%). Note 9: Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. The input voltage = VID = 500mV, K28.5 pattern at 1.5 Gbps, tr = tf = 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101). Note 10: Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture Jitter has been subtracted. The input voltage = VID = 500mV, 223-1 PRBS pattern at 1.5 Gbps, tr = tf = 50ps (20% to 80%). www.national.com 4 DS90LV004 Feature Descriptions OUTPUT CHARACTERISTICS The output characteristics of the DS90LV004 have been optimized for point-to-point backplane and cable applications, and are not intended for multipoint or multidrop signaling. POWERDOWN MODE The PWDN input activates a hardware powerdown mode. When the powerdown mode is active (PWDN=L), all input and output buffers and internal bias circuitry are powered off and disabled. Outputs are tri-stated in powerdown mode. When exiting powerdown mode, there is a delay associated with turning on bandgap references and input/output buffer circuits as indicated in the LVDS Output Switching Characteristics PRE-EMPHASIS Pre-emphasis dramatically reduces ISI jitter from long or lossy transmission media. Two pins are used to select the pre-emphasis level for all outputs: off, low, medium, or high. Pre-emphasis Control Selection Table PEM1 0 0 1 1 PEM0 0 1 0 1 Pre-Emphasis Off Low Medium High INPUT FAILSAFE BIASING External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors should be in the 5k to 15k range to minimize loading and waveform distortion to the driver. The common-mode bias point ideally should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal circuitry. Please refer to application note AN1194 "Failsafe Biasing of LVDS Interfaces" for more information. 5 www.national.com DS90LV004 Typical Performance Characteristics Power Supply Current vs. Bit Data Rate Total Jitter (TJ) vs. Bit Data Rate 20146641 20146642 Dynamic power supply current was measured while running a clock or PRBS 223-1 pattern with all 4 channels active. VCC = 3.3V, TA = +25C, VID = 0.5V, VCM = 1.2V Total Jitter measured at 0V differential while running a PRBS 223-1 pattern with a single channel active. VCC = 3.3V, TA = +25C, VID = 0.5V, 0% Pre-emphasis Total Jitter (TJ) vs. Temperature Positive Edge Transition vs. Pre-emphasis Level 20146644 20146643 Total Jitter measured at 0V differential while running a PRBS 223-1 pattern with a single channel active. VCC = 3.3V, VID = 0.5V, VCM = 1.2V, 1.5 Gbps data rate, 0% Pre-emphasis FIGURE 1. Typical Performance Characteristics of the DS90LV004 www.national.com 6 DS90LV004 4-Channel LVDS Buffer/Repeater with Pre-Emphasis Physical Dimensions inches (millimeters) unless otherwise noted 48-TQFP NS Package Number VBC48a Order Number DS90LV004TVS (250 piece Tray) National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ``Banned Substances'' as defined in CSP-9-111S2. Leadfree products are RoHS compliant. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Francais Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. |
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